Vervain, LLC v. Kingston Technology Company, Inc.
1:24-cv-00254
Overview
Case Number
1:24-cv-00254
Filing Date
2024-03-07
Status
Litigation filed
Court
District Court, W.D. Texas
Nature of Suit
830 Patent
Parties
Defendant
Plaintiff
Court & Judges
Court
District Court, W.D. Texas
Presiding Judge
Alan D. Albright
Patents Involved
There are 11 patents involved in this case.
| Application Number | Patent Number | External Links |
|---|---|---|
| - | US8891298 | |
| - | US9196385 | |
| - | US9997240 | |
| - | US10950300 | |
| - | US11830546 | |
| - | US11854612 | |
| - | US11967369 | |
| - | US11967370 | |
| - | US8194452 | |
| - | US7855916 | |
| - | US6456528 |
Docket Entries
COMPLAINT ( Filing fee $ 405 receipt number ATXWDC-18506570), filed by Vervain, LLC. (Attachments: # 1 Exhibit A, # 2 Exhibit B, # 3 Exhibit C, # 4 Exhibit D, # 5 Exhibit E, # 6 Exhibit F, # 7 Exhibit G, # 8 Exhibit H, # 9 Exhibit I, # 10 Exhibit J, # 11 Exhibit K, # 12 Exhibit L, # 13 Exhibit M, # 14 Exhibit N, # 15 Exhibit O, # 16 Exhibit P, # 17 Exhibit Q, # 18 Exhibit R, # 19 Exhibit S, # 20 Exhibit T, # 21 Exhibit U, # 22 Exhibit V, # 23 Exhibit W, # 24 Exhibit X, # 25 Exhibit Y, # 26 Exhibit Z, # 27 Exhibit AA, # 28 Exhibit BB, # 29 Exhibit CC, # 30 Exhibit DD, # 31 Exhibit EE, # 32 Exhibit FF, # 33 Exhibit GG, # 34 Exhibit HH, # 35 Exhibit II, # 36 Exhibit JJ, # 37 Exhibit KK, # 38 Exhibit LL, # 39 Exhibit MM, # 40 Exhibit NN, # 41 Exhibit OO, # 42 Exhibit PP, # 43 Exhibit QQ, # 44 Exhibit RR, # 45 Exhibit SS, # 46 Exhibit TT, # 47 Exhibit UU, # 48 Exhibit VV, # 49 Exhibit WW, # 50 Exhibit XX, # 51 Exhibit YY, # 52 Civil Cover Sheet)(Whitehurst, Alan) (Entered: 03/07/2024)
2024-03-07
1
If ordered by the court, all referrals and consents in this case will be assigned to Magistrate Judge Mark Lane. (kp)
2024-03-07
1
No Actions
Case assigned to Judge Alan D Albright. CM WILL NOW REFLECT THE JUDGE INITIALS AS PART OF THE CASE NUMBER. PLEASE APPEND THESE JUDGE INITIALS TO THE CASE NUMBER ON EACH DOCUMENT THAT YOU FILE IN THIS CASE. (kp)
2024-03-07
1
No Actions
DEMAND for Trial by Jury by Vervain, LLC. (kp)
2024-03-07
1
No Actions
REQUEST FOR ISSUANCE OF SUMMONS by Vervain, LLC. (Attachments: # 1 summons, # 2 summons)(Whitehurst, Alan) (Entered: 03/08/2024)
2024-03-08
1
Notice of Filing of Patent/Trademark Form (AO 120). AO 120 forwarded to the Director of the U.S. Patent and Trademark Office. (Whitehurst, Alan) (Entered: 03/08/2024)
2024-03-08
1
RULE 7 DISCLOSURE STATEMENT filed by Vervain, LLC. (Whitehurst, Alan) (Entered: 03/08/2024)
2024-03-08
1
Summons Issued as to Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (kp) (Entered: 03/08/2024)
2024-03-08
1
Case Assigned/Reassigned
2024-03-08
1
No Actions
To be Referred to AU Mag Judge
2024-03-08
1
No Actions
Jury Demand
2024-03-08
1
No Actions
SUMMONS Returned Executed by Vervain, LLC. All Defendants. (Whitehurst, Alan) (Entered: 03/11/2024)
2024-03-11
1
NOTICE of Attorney Appearance by George Andrew Lever Rosbrook on behalf of Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. Attorney George Andrew Lever Rosbrook added to party Kingston Digital, Inc.(pty:dft), Attorney George Andrew Lever Rosbrook added to party Kingston Technology Company, Inc.(pty:dft), Attorney George Andrew Lever Rosbrook added to party Kingston Technology Corporation(pty:dft) (Rosbrook, George Andrew) (Entered: 03/20/2024)
2024-03-20
1
NOTICE of Extension of Time to File Answer or Otherwise Respond by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit A - Proposed Order)(Rosbrook, George Andrew) Modified on 3/28/2024 (dm). (Entered: 03/22/2024)
2024-03-22
1
NOTICE of Attorney Appearance by Cono A. Carrano on behalf of Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. Attorney Cono A. Carrano added to party Kingston Digital, Inc.(pty:dft), Attorney Cono A. Carrano added to party Kingston Technology Company, Inc.(pty:dft), Attorney Cono A. Carrano added to party Kingston Technology Corporation(pty:dft) (Carrano, Cono) (Entered: 05/08/2024)
2024-05-08
1
AMENDED COMPLAINT against All Defendants amending, filed by Vervain, LLC. (Attachments: # 1 Exhibit A, # 2 Exhibit B, # 3 Exhibit C, # 4 Exhibit D, # 5 Exhibit E, # 6 Exhibit F, # 7 Exhibit G, # 8 Exhibit H, # 9 Exhibit I, # 10 Exhibit J, # 11 Exhibit K, # 12 Exhibit L, # 13 Exhibit M, # 14 Exhibit N, # 15 Exhibit O, # 16 Exhibit P, # 17 Exhibit Q, # 18 Exhibit R, # 19 Exhibit S, # 20 Exhibit T, # 21 Exhibit U, # 22 Exhibit V, # 23 Exhibit W, # 24 Exhibit X, # 25 Exhibit Y, # 26 Exhibit Z, # 27 Exhibit AA, # 28 Exhibit BB, # 29 Exhibit CC, # 30 Exhibit DD, # 31 Exhibit EE, # 32 Exhibit FF, # 33 Exhibit GG, # 34 Exhibit HH, # 35 Exhibit II, # 36 Exhibit JJ, # 37 Exhibit KK, # 38 Exhibit LL, # 39 Exhibit MM, # 40 Exhibit NN, # 41 Exhibit OO, # 42 Exhibit PP, # 43 Exhibit QQ, # 44 Exhibit RR, # 45 Exhibit SS, # 46 Exhibit TT, # 47 Exhibit UU, # 48 Exhibit VV, # 49 Exhibit WW, # 50 Exhibit ZZ, # 51 Exhibit AAA)(Whitehurst, Alan) (Entered: 05/10/2024)
2024-05-10
1
Unopposed MOTION for Extension of Time to File Answer re 10 Amended Complaint,,,, by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Proposed Order)(Rosbrook, George Andrew) (Entered: 05/16/2024)
2024-05-16
1
NOTICE of Unopposed Extension of Time to Answer or Otherwise Respond by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation re 10 Amended Complaint,,,, (Rosbrook, George Andrew) (Entered: 05/21/2024)
2024-05-21
1
Sealed Motion Defendants' Opposed Motion to Dismiss for Improper Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation (Attachments: # 1 Exhibit 2 - Declaration of Rick Webb) (Carrano, Cono) (Entered: 06/07/2024)
2024-06-07
1
ATTACHMENT to 13 Sealed Motion Defendants' Opposed Motion to Dismiss for Improper Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Declaration of George Andrew Lever Rosbrook, # 2 Exhibit A - to Rosbrook Declaration Email Exchange between Counsel, # 3 Exhibit A - to Webb's Declaration - Moveout Checklist, # 4 Exhibit B - to Webb's Declaration - Job Posting)(Carrano, Cono) (Entered: 06/07/2024)
2024-06-07
1
NOTICE of Venue Discovery Regarding Defendants' Opposed Motion to Dismiss by Vervain, LLC (Whitehurst, Alan) (Entered: 06/10/2024)
2024-06-10
1
Redacted Copy of 13 Sealed Motion Defendants' Opposed Motion to Dismiss for Improper Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 2 - Declaration of Rick Webb)(Carrano, Cono) (Entered: 06/14/2024)
2024-06-14
1
NOTICE Case Readiness Status Report by Vervain, LLC (Whitehurst, Alan) (Entered: 06/14/2024)
2024-06-14
1
Proposed Scheduling Order Joint Motion for Entry of Scheduling Order by Vervain, LLC. (Whitehurst, Alan) (Entered: 07/12/2024)
2024-07-12
1
SCHEDULING ORDER: Pretrial Conference set for 11/18/2025 at 9:00 AM before Judge Alan D Albright, Jury Selection and Trial set for 12/8/2025 at 9:30 AM before Judge Alan D Albright, Markman Hearing set for 12/5/2024, Amended Pleadings due by 3/28/2025, Discovery due by 7/7/2025, Joinder of Parties due by 1/17/2025, Motions due by 9/12/2025. Signed by Judge Alan D Albright. (dm) (Entered: 07/15/2024)
2024-07-15
1
MOTION to Transfer Case Defendants' Opposed Motion to Transfer Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Second Declaration of Rick Webb, # 2 Exhibit 2 - Amd and Restated Articles of Incorporation for Silicon Motion Inc., # 3 Exhibit 3 - Silicon Motion website, # 4 Exhibit 4 - Excerpts from Phison website, # 5 Exhibit 5 - Petition for IPR No. 2021-01547, # 6 Exhibit 6 - Institution Decision IPR No. 2021-00547, # 7 Exhibit 7 - Institution Decision IPR No. 2021-01548, # 8 Exhibit 8 - Moshayedi Website, # 9 Exhibit 9 - US Patent App. No. 2008/0140918, # 10 Exhibit 10 - US Patent App. No. 2011/0099460, # 11 Exhibit 11 - Western Digital's Statement in Vervain v. Western Digital, # 12 Exhibit 12 - Articles of Incorporation for SanDisk, LLC, # 13 Exhibit 13 - Wester Digital Joint Pretrial Order in, # 14 Exhibit 14 - Complaint for Patent Infringement in Vervain v. Micron, # 15 Exhibit 15 - First Amd Complaint for Patent Infringement in Vervain v. Phison, # 16 Exhibit 16 - Caseload Statistics, # 17 Exhibit 17 - Declaration of George Andrew Lever Rosbrook)(Carrano, Cono) (Entered: 07/19/2024)
2024-07-19
1
NOTICE of Appearance of Counsel Christian Dorman by Vervain, LLC (Whitehurst, Alan) (Entered: 08/05/2024)
2024-08-05
1
Unopposed MOTION for Leave to Exceed Page Limitation, Additional Terms to be Construed and for Extension of Time by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Proposed Order Order)(Rosbrook, George Andrew) (Entered: 10/02/2024)
2024-10-02
1
Text Order GRANTING IN PART AND DENYING IN PART 22 Motion for Leave to File Excess Pages and extend deadlines entered by Judge Alan D Albright. The motion to extend deadlines is GRANTED. As noted in the Joint Proposed extensions, Defendants opening brief deadline is moved from 10/4/2024 to 10/7/2024. Plaintiffs responsive brief deadline is moved from 10/25/2024 to 10/28/2024 Defendants reply brief deadline is moved from 11/8/2024 to 11/11/2024 Plaintiffs sur-reply brief deadline is moved from 11/22/2024 to 11/25/2024. The motion for leave to exceed page limitations is DENIED. The motion requesting briefing for two additional claim terms is GRANTED. (This is a text-only entry generated by the court. There is no document associated with this entry.) (cblc)
2024-10-03
1
No Actions
Order on Motion for Leave to File Excess Pages
2024-10-03
1
No Actions
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
1
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
Opening Claim Construction Brief by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Proposed Terms and Constructions, # 2 Exhibit 2 - Expert Declaration and CV of Andrew Wolfe, Ph.D., # 3 Exhibit 3 - U.S. Patent No. 8,891,298 to Rao, # 4 Exhibit 4 - U.S. Patent No. 9,196,385 to Rao, # 5 Exhibit 5 - U.S. Patent No. 9,997,240 to Rao, # 6 Exhibit 6 - U.S. Patent No. 10,950,300 to Rao, # 7 Exhibit 7 - U.S. Patent No. 11,830,546 to Rao, # 8 Exhibit 8 - U.S. Patent No. 11,854,612 to Rao, # 9 Exhibit 9 - U.S. Patent No. 11,967,369 to Rao, # 10 Exhibit 10 - U.S. Patent No. 11,967,370 to Rao, # 11 Exhibit 11 - U.S. Patent No. 8,194,452 to Rao, # 12 Exhibit 12 - U.S. Patent No. 7,855,916 to Rao, # 13 Exhibit 13 - U.S. Patent No. 6,456,528 to Chen, # 14 Exhibit 14 - U.S. Patent Appl. Pub. No. 2010/0172179 to Gorobets, # 15 Exhibit 15 - U.S. Patent Appl. Pub. No. 2011/0099460 to Dusija, # 16 Exhibit 16 - U.S. Patent Appl. Pub. No. 2009/0172267 to Oribe, # 17 Exhibit 17 - U.S. Patent Appl. Pub. No. 2010/0318879 to Yu, # 18 Exhibit 18 - 298 Patent Prosecution History Excerpts, # 19 Exhibit 19 - 385 Patent Prosecution History Excerpts, # 20 Exhibit 20 - 240 Patent Prosecution History Excerpts, # 21 Exhibit 21 - 300 Patent Prosecution History Excerpts, # 22 Exhibit 22 - 546 Patent Prosecution History Excerpts, # 23 Exhibit 23 - 612 Patent Prosecution History Excerpts, # 24 Exhibit 24 - 369 Patent Prosecution History Excerpts, # 25 Exhibit 25 - 370 Patent Prosecution History Excerpts, # 26 Exhibit 26 - Exhibit A-1 of Vervains Preliminary Infringement Contentions to Phison, # 27 Exhibit 27 - Exhibit A-4 of Vervains Preliminary Infringement Contentions to Phison, # 28 Exhibit 28 - Manual of Patent Examining Procedure (MPEP) § 2173.05(p)(II), # 29 Exhibit 29 - Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 30 Exhibit 30 - Tue-Sung Jung et al., A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications, 31 IEEE J. Solid-State Circuits (Nov. 1996) (Jung), # 31 Exhibit 31 - Greg Atwood et al., Intel StrataFlash Memory Technology Overview, INTEL TECHNOLOGY J. (Q4 1997) (Atwood), # 32 Exhibit 32 - Ken Takeuchi et al., A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, 33 IEEE J. SOLID-STATE CIRCUITS (Aug. 1998) (Takeuchi), # 33 Exhibit 33 - Taehee Cho et al., A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, 36 IEEE J. SOLID-STATE CIRCUITS (Nov. 2001) (Cho), # 34 Exhibit 34 - Taeho Kgil et al., Improving NAND Flash Based Disk Caches, International Symposium on Computer Architecture (June 2008) (Kgil), # 35 Exhibit 35 - Se Jin Kwon et al., FTL algorithms for NAND-type flash memories (Mar. 2011) (Kwon), # 36 Exhibit 36 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Paper), USENIX (Feb. 2010), # 37 Exhibit 37 - Boboila & Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis (Slides), USENIX (Feb. 2010), # 38 Exhibit 38 - Micron TN-29-61: Wear Leveling in NAND Flash Memory (Apr. 2011), # 39 Exhibit 39 - Duann, SLC & MLC Hybrid Presentation (Aug. 2008), # 40 Exhibit 40 - Excerpts from Microsoft Computer Dictionary (5th ed. 2002), # 41 Exhibit 41 - Excerpts from Wiley Electrical and Electronics Engineering Dictionary (1st ed. 2004), # 42 Exhibit 42 - Excerpts from The Facts on File Dictionary of Computer Science (Rev. ed. 2006), # 43 Exhibit 43 - Excerpts from Principles of Information Systems (9th ed. 2010), # 44 Exhibit 44 - Excerpts from Database System Concepts (Custom ed. 2010), # 45 Exhibit 45 - Declaration of Sunil P. Khatri, Ph.D., Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Dec. 3, 2021), ECF No. 30-2., # 46 Exhibit 46 - Claim Construction Order, Vervain, LLC v. Micron, No. 6:21-cv-487 (W.D. Tex. Jan. 24, 2022), ECF No. 42., # 47 Exhibit 47 - Claim Construction Order, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-488 (W.D. Tex. Jan. 24, 2022), ECF No. 41., # 48 Exhibit 48 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin in Support of Defendants' Opening Claim Construction Brief)(Carrano, Cono) (Entered: 10/07/2024)
2024-10-07
2
NOTICE of Post Grant Review Filing for U.S. Patent Nos. 11,830,546 and 11,854,612 by Vervain, LLC (Whitehurst, Alan) (Entered: 10/08/2024)
2024-10-08
1
Sealed Document: Vervain's Response to Defendants' Motion to Dismiss for Improper Venue of 13 Sealed Motion Defendants' Opposed Motion to Dismiss for Improper Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation by Vervain, LLC (Attachments: # 1 Declaration of Alan L. Whitehurst, # 2 Exhibit 1 [FILED UNDER SEAL], # 3 Exhibit 2 [FILED UNDER SEAL], # 4 Exhibit 3 [FILED UNDER SEAL], # 5 Exhibit 4 [FILED UNDER SEAL], # 6 Exhibit 5 [FILED UNDER SEAL], # 7 Exhibit 6 [FILED UNDER SEAL], # 8 Exhibit 7 [FILED UNDER SEAL], # 9 Exhibit 8 [FILED UNDER SEAL]) (Whitehurst, Alan) (Entered: 10/09/2024)
2024-10-09
1
Sealed Document: Vervain's Response to Defendants' Motion to Transfer Venue of 20 MOTION to Transfer Case Defendants' Opposed Motion to Transfer Venue by Vervain, LLC (Attachments: # 1 Declaration of Alan L. Whitehurst, # 2 Exhibit 1 [FILED UNDER SEAL], # 3 Exhibit 2 [FILED UNDER SEAL]) (Whitehurst, Alan) (Entered: 10/09/2024)
2024-10-09
1
ATTACHMENT Public Exhibits 3-8 to Vervain's Response to Defendants' Motion to Transfer Venue to 26 Sealed Document, by Vervain, LLC. (Attachments: # 1 Exhibit 3, # 2 Exhibit 4, # 3 Exhibit 5, # 4 Exhibit 6, # 5 Exhibit 7, # 6 Exhibit 8)(Whitehurst, Alan) (Entered: 10/09/2024)
2024-10-09
1
Redacted Public Version of 25 Sealed Document,, by Vervain, LLC. (Whitehurst, Alan) (Entered: 10/16/2024)
2024-10-16
1
Redacted Public Version of 26 Sealed Document, by Vervain, LLC. (Whitehurst, Alan) (Entered: 10/16/2024)
2024-10-16
1
Sealed Document: Kingston's Reply in Support of 13 Sealed Motion Defendants' Opposed Motion to Dismiss for Improper Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation (Attachments: # 1 Exhibit Ex. 1 - Offer Letter, # 2 Exhibit Ex. 2 - Specification) (Carrano, Cono) (Entered: 10/16/2024)
2024-10-16
1
Redacted Copy of 30 Sealed Document, by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Carrano, Cono) (Entered: 10/23/2024)
2024-10-23
1
Sealed Document: Defendants' Reply in Support of Defendants Motion to Transfer Venue of 20 MOTION to Transfer Case Defendants' Opposed Motion to Transfer Venue by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation (Carrano, Cono) (Entered: 10/23/2024)
2024-10-23
1
ATTACHMENT Public Exhibits 1 and 2 to Defendants' Reply in Support of Defendants' Motion to Transfer Venue to 32 Sealed Document, by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Declaration of Tracy Chang, # 2 Exhibit 2 - Phison Controller Chart)(Carrano, Cono) (Entered: 10/23/2024)
2024-10-23
1
STATUS REPORT Regarding Completion of Briefing on Venue Transfer Motions by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Carrano, Cono) (Entered: 10/24/2024)
2024-10-24
1
Opening Claim Construction Brief by Vervain, LLC Responsive Opening Claim Construction Brief. (Attachments: # 1 Exhibit 1, # 2 Exhibit 2, # 3 Exhibit 3, # 4 Exhibit 4, # 5 Exhibit 5, # 6 Exhibit 6, # 7 Exhibit 7, # 8 Exhibit 8, # 9 Exhibit 9, # 10 Exhibit 10, # 11 Exhibit 11, # 12 Exhibit 12, # 13 Exhibit 13, # 14 Exhibit 14, # 15 Exhibit 15, # 16 Exhibit 16, # 17 Exhibit 17, # 18 Exhibit 18, # 19 Exhibit 19, # 20 Exhibit 20, # 21 Exhibit 21, # 22 Exhibit 22, # 23 Exhibit 23, # 24 Exhibit 24, # 25 Exhibit 25, # 26 Exhibit 26, # 27 Exhibit 27, # 28 Exhibit 28, # 29 Exhibit 29, # 30 Exhibit 30, # 31 Exhibit 31, # 32 Exhibit 32, # 33 Exhibit 33, # 34 Exhibit 34, # 35 Exhibit 35, # 36 Declaration of Alan L. Whitehurst)(Whitehurst, Alan) (Entered: 10/28/2024)
2024-10-28
1
Opposed MOTION to Strike New Evidence and Argument Raised in Kingston's Reply Briefing by Vervain, LLC. (Attachments: # 1 Declaration of Alan L. Whitehurst, # 2 Exhibit A, # 3 Proposed Order)(Whitehurst, Alan) (Entered: 10/29/2024)
2024-10-29
1
Redacted Copy of Dfts' Reply in Support of Dfts' Motion to Transfer Venue of 32 Sealed Document, by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Carrano, Cono) (Entered: 10/30/2024)
2024-10-30
1
STATUS REPORT Regarding Completion of Briefing on Venue Transfer Motions by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Carrano, Cono) (Entered: 11/07/2024)
2024-11-07
1
BRIEF Defendants' Reply Claim Construction Brief regarding 35 Claim Construction Brief,,, by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. (Attachments: # 1 Exhibit 1 - Excerpts from Rino Micheloni et al., Inside NAND Flash Memories (Aug. 2010) (Micheloni), # 2 Exhibit 2 - Western Digitals Opposition to Vervains Motion for Partial Summary Judgment, Vervain, LLC v. Western Digital Corp., No. 6:21-cv-00488 (W.D. Tex. Apr. 25, 2023), ECF No. 133, # 3 Exhibit 3 - Deposition of Sunil P. Khatri, Ph.D., Micron Tech., Inc. v. Vervain, LLC, IPR2021-01547 (U.S.P.T.O. Sept. 1, 2022), # 4 Exhibit 4 - Markman Hearing Transcript, Vervain, LLC v. Micron Tech., Inc., No. 6:21-cv-00487 (W.D. Tex. Feb. 15, 2022), ECF No. 50, # 5 Exhibit 5 - Declaration of George Andrew Lever Rosbrook and Douglas E. Chin)(Carrano, Cono) (Entered: 11/11/2024)
2024-11-11
1
Response in Opposition to Motion, filed by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation, re 36 Opposed MOTION to Strike New Evidence and Argument Raised in Kingston's Reply Briefing filed by Plaintiff Vervain, LLC (Attachments: # 1 Exhibit Declaration of George Rosbrook)(Carrano, Cono) (Entered: 11/12/2024)
2024-11-12
1
REPLY to Response to Motion, filed by Vervain, LLC, re 36 Opposed MOTION to Strike New Evidence and Argument Raised in Kingston's Reply Briefing filed by Plaintiff Vervain, LLC (Whitehurst, Alan) (Entered: 11/19/2024)
2024-11-19
1
BRIEF Plaintiff's Sur-reply Claim Construction Brief regarding 39 Brief,,, by Vervain, LLC. (Whitehurst, Alan) (Entered: 11/25/2024)
2024-11-25
1
NOTICE of Filing Joint Claim Construction Statement by Vervain, LLC (Whitehurst, Alan) (Entered: 11/27/2024)
2024-11-27
1
ORDER, ( Markman Hearing via Zoom reset for 1/9/2025 at 10:00 AM before Judge Alan D Albright,). Signed by Judge Alan D Albright. (dm) (Entered: 12/03/2024)
2024-12-03
1
ORDER, ( Motion Hearing via Zoom set for 12/5/2024 at 9:30 AM Regarding Motion to Dismiss, before Judge Alan D Albright,). Signed by Judge Alan D Albright. (dm) (Entered: 12/03/2024)
2024-12-03
1
Minute Entry for proceedings held before Judge Alan D Albright: Motion Hearing held on 12/5/2024 re 13 Sealed Motion Defendants' Opposed Motion to Dismiss for Improper Venue. Parties announce ready, statements and arguments of counsel heard, motion denied. Written order forthcoming. (Minute entry documents are not available electronically.). (Court Reporter Kristie Davis.)(dm) (Entered: 12/06/2024)
2024-12-05
1
12-5-24 Motions Hearing Sealed Transcript filed (This transcript is not available electronically) (kd) (Entered: 12/10/2024)
2024-12-10
1
ORDER, ( Zoom Markman Hearing set for 1/9/2025 at 11:00 AM before Judge Alan D Albright,). Signed by Judge Alan D Albright. (dm) (Entered: 12/16/2024)
2024-12-16
1
MOTION to Appear Pro Hac Vice by Cono A. Carrano Motion for Admission Pro Hac Vice of Brock F. Wilson ( Filing fee $ 100 receipt number ATXWDC-19595695) by on behalf of Kingston Technology Company, Inc., Kingston Digital, Inc., Kingston Technology Corporation. (Attachments: # 1 Proposed Order Order Granting Mtn for Admission Pro Hac Vice)(Carrano, Cono) (Entered: 12/18/2024)
2024-12-18
1
Defendants' Answer and Defenses to Vervain, LLC's First Amended Complaint for Patent Infringement ANSWER to 10 Amended Complaint,,,, with Jury Demand by Kingston Technology Company, Inc., Kingston Digital, Inc., Kingston Technology Corporation.(Carrano, Cono) (Entered: 12/19/2024)
2024-12-19
1
ORDER GRANTING 49 Motion to Appear Pro Hac Vice for Attorney Brock F. Wilson for Kingston Digital, Inc.,Brock F. Wilson for Kingston Technology Company, Inc.,Brock F. Wilson for Kingston Technology Corporation. Pursuant to our Administrative Policies and Procedures for Electronic Filing, the attorney hereby granted to practice pro hac vice in this case must register for electronic filing with our court within 10 days of this order. Registration is managed by the PACER Service Center Signed by Judge Alan D Albright. (pg) (Entered: 12/20/2024)
2024-12-19
1
ORDER, ( Markman Hearing reset for 1/9/2025 at 9:30 AM before Judge Alan D Albright,). Signed by Judge Alan D Albright. (dm) (Entered: 01/02/2025)
2025-01-02
1
NOTICE of Filing Notice of Inter Partes Review Filings for US Patent Nos. 8,891,298, 9,196,385, 9,997,240 and 10,950,300 by Vervain, LLC (Whitehurst, Alan) (Entered: 01/03/2025)
2025-01-03
1
NOTICE of Filing Notice of Post-Grant Review Filings for US Patent Nos. 11,967,369 and 11,967,370 by Vervain, LLC (Whitehurst, Alan) (Entered: 01/03/2025)
2025-01-03
1
ORDER, ( Zoom Markman Hearing set for 1/31/2025 at 3:00 PM before Judge Alan D Albright,). Signed by Judge Alan D Albright. (dm) (Entered: 01/28/2025)
2025-01-28
1
ORDER GRANTING 36 Motion to Strike ; DENYING 20 Motion to Transfer Case. Signed by Judge Alan D Albright. (dm) (Entered: 01/28/2025)
2025-01-28
1
ORDER, ( Public Zoom Markman Hearing reset for 2/6/2025 at 1:30 PM before Judge Alan D Albright,). Signed by Judge Alan D Albright. (dm) (Entered: 01/29/2025)
2025-01-29
1
NOTICE Joint Notice Extending Deadlines by Vervain, LLC (Whitehurst, Alan) (Entered: 01/29/2025)
2025-01-29
1
Sealed Order Denying Motion to Dismiss. Signed by Judge Alan D Albright. (dm) (Entered: 02/05/2025)
2025-02-05
1
MOTION to Appear Pro Hac Vice by Cono A. Carrano Motion for Admission Pro Hac Vice of Ryan S. Stronczer ( Filing fee $ 100 receipt number ATXWDC-19754951) by on behalf of Kingston Technology Company, Inc., Kingston Digital, Inc., Kingston Technology Corporation. (Attachments: # 1 Proposed Order Order Granting Mtn for Admission Pro Hac Vice)(Carrano, Cono) (Entered: 02/05/2025)
2025-02-05
1
CORRECTED ORDER Granting 60 MOTION to Appear Pro Hac Vice as to Ryan S. Stronczer ( Filing fee $ 100 receipt number ATXWDC-19754951) filed by Kingston Digital, Inc., Kingston Technology Company, Inc., Kingston Technology Corporation. Pursuant to our Administrative Policies and Procedures for Electronic Filing, the attorney hereby granted to practice pro hac vice in this case must register for electronic f iling with our court within 10 days of this order. Registration is managed by the PACER Service Center entered by Judge Alan D Albright. (This is a text-only entry generated by the court. Signed by Judge Alan D Albright. (dm) (Entered: 02/06/2025)
2025-02-06
1
Minute Entry for proceedings held before Judge Alan D Albright: PUBLIC ZOOM MARKMAN VERVAIN V KINGSTON 1.24.254 held on 2/6/2025. Written Order Forthcoming. (Minute entry documents are not available electronically.) (Court Reporter Kristie Davis.)(pg) (Entered: 02/10/2025)
2025-02-06
1
Text Order GRANTING 60 Motion to Appear Pro Hac Vice for Cono A. Carrano. Pursuant to our Administrative Policies and Procedures for Electronic Filing, the attorney hereby granted to practice pro hac vice in this case must register for electronic filing with our court within 10 days of this order. Registration is managed by the PACER Service Center entered by Judge Alan D Albright. (This is a text-only entry generated by the court. There is no document associated with this entry.) (cblc)
2025-02-06
1
No Actions
Order on Motion to Appear Pro Hac Vice
2025-02-06
1
No Actions
Transcript Filed
2025-02-17
1
Withdraw As Attorney
2025-02-28
1
Appear Pro Hac Vice
2025-02-28
1
Order on Motion to Appear Pro Hac Vice
2025-03-03
1
Appear Pro Hac Vice
2025-03-06
1
Appear Pro Hac Vice
2025-03-06
1
Order on Motion to Appear Pro Hac Vice
2025-03-07
1
Order on Motion to Appear Pro Hac Vice
2025-03-07
1
Confidentiality and Protective Order
2025-03-19
1
Protective Order AND ~Util - Terminate Motions
2025-03-20
1
Appear Pro Hac Vice
2025-06-26
1
Amend/Correct (Not Judgment)
2025-06-26
1
Order on Motion to Appear Pro Hac Vice
2025-06-27
1
Scheduling Order AND ~Util - Terminate Motions
2025-07-07
1
Appear Pro Hac Vice
2025-07-25
1
Order on Motion to Appear Pro Hac Vice
2025-07-28
1
Amend/Correct (Not Judgment)
2025-08-18
1
Scheduling Order AND ~Util - Terminate Motions
2025-09-17
1
Order on Motion to Withdraw as Attorney
2025-09-17
1
No Actions
Amend/Correct (Not Judgment)
2025-09-29
1
Scheduling Order AND ~Util - Terminate Motions
2025-09-30
1
Order AND ~Util - Set Hearings
2025-09-30
1
Discovery Hearing
2025-10-07
1
Transcript of Sealed or In Camera Proceedings Filed
2025-10-08
1
Leave to File Document
2025-10-14
1
Sealed Document - Patent Cases only
2025-10-14
1
Sealed Document - Patent Cases only
2025-10-14
1
Order on Motion for Leave to File
2025-10-15
1
No Actions
Notice
2025-10-18
1
Amend/Correct (Not Judgment)
2025-10-31
1
Scheduling Order
2025-11-03
1
Sealed Document
2025-11-04
1
No Actions
Notice
2025-11-21
1
Amend/Correct (Not Judgment)
2025-11-24
1
Scheduling Order
2025-11-25
1
Notice of Attorney Appearance
2026-01-08
1
Appear Pro Hac Vice
2026-01-08
1
Appear Pro Hac Vice
2026-01-08
1
Order on Motion to Appear Pro Hac Vice
2026-01-09
1
Order on Motion to Appear Pro Hac Vice
2026-01-09
1
Appear Pro Hac Vice
2026-01-22
1
Amend/Correct (Not Judgment)
2026-01-23
1
Order on Motion to Appear Pro Hac Vice
2026-01-26
1
Scheduling Order
2026-01-28
1
Appear Pro Hac Vice
2026-02-19
1
Notice of Change of Address
2026-02-19
1
Appear Pro Hac Vice
2026-02-23
1
Appear Pro Hac Vice
2026-02-23
1
Order on Motion to Appear Pro Hac Vice
2026-02-24
1
Order on Motion to Appear Pro Hac Vice
2026-02-24
1
Order on Motion to Appear Pro Hac Vice
2026-02-24
1
Notice
2026-03-11
1
Certificate of Service
2026-03-11
1
Order
2026-03-12
1
Order on Motion to Amend/Correct
2026-03-12
1
No Actions
Sealed Document
2026-03-12
1
No Actions
Redacted Copy
2026-03-18
1
Status Report
2026-03-19
1
Exclude
2026-03-20
1
Notice of Filing
2026-03-21
1
Certificate of Service
2026-03-21
1
Appear Pro Hac Vice
2026-03-23
1
Sealed Motion
2026-03-23
1
No Actions
Order on Motion to Appear Pro Hac Vice
2026-03-24
1
Motion for Leave to File Sealed Document AND Sealed Motion
2026-03-24
1
No Actions
Sealed Motion
2026-03-24
1
No Actions
Deficiency Notice
2026-03-25
1
No Actions
Notice of Filing
2026-03-26
1
Notice of Filing
2026-03-26
1
Status Report
2026-03-26
1
Sealed Motion
2026-03-26
1
No Actions
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Status Report
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Redacted Copy
2026-03-27
1
Notice
2026-04-01
1
Certificate of Service
2026-04-06
1
Miscellaneous Relief
2026-04-07
1
Sealed Document
2026-04-07
1
No Actions
Notice
2026-04-08
1
Notice
2026-04-08
1
Notice of Filing
2026-04-08
1
Notice
2026-04-08
1
Notice of Filing
2026-04-08
1
Notice of Filing
2026-04-08
1
Response to Motion
2026-04-08
1
Sealed Document
2026-04-08
1
No Actions
Sealed Document
2026-04-09
1
No Actions
Sealed Document
2026-04-10
1
No Actions
Notice of Correction
2026-04-10
1
No Actions
Notice of Filing
2026-04-13
1
Notice of Filing
2026-04-13
1
Notice of Filing - Redacted Public Version
2026-04-13
1
Sealed Document
2026-04-13
1
No Actions
Notice
2026-04-14
1
Notice
2026-04-15
1
Response in Support of Motion
2026-04-15
1
Sealed Document
2026-04-16
1
No Actions
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-17
1
Redacted Copy
2026-04-21
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Redacted Copy
2026-04-22
1
Sealed Document
2026-04-22
1
No Actions
Order AND ~Util - Terminate Hearings
2026-04-23
1
Notice of Filing
2026-04-24
1
Notice
2026-04-24
1
Deficiency Notice
2026-04-27
1
No Actions
Sealed Motion
2026-04-27
1
No Actions
Stipulation
2026-04-29
1
Redacted Copy
2026-05-01
1
Redacted Copy
2026-05-01
1
Notice
2026-05-01
1
Sealed Document
2026-05-04
1
No Actions
Redacted Copy
2026-05-08
1
Redacted Copy
2026-05-08
1
Sealed Document
2026-05-08
1
No Actions
Redacted Copy
2026-05-14
1
Redacted Copy
2026-05-14
1
Claim Construction Order
2026-05-19
1
Withdraw As Attorney
2026-06-12
1
Order on Motion to Withdraw as Attorney
2026-06-15
1
No Actions
Sealed Motion
2026-07-07
1
No Actions
Redacted Copy
2026-07-13
1
Notice of Filing
2026-07-13
1
Sealed Document
2026-07-14
1
No Actions
Redacted Copy
2026-07-20
1
Reply to Response to Motion
2026-07-20
1
Withdraw As Attorney
2026-07-21
1
Order on Motion to Withdraw as Attorney
2026-07-22
1
No Actions
Order
2026-08-06
1
Withdraw As Attorney
2026-08-26
1
Order on Motion to Withdraw as Attorney
2026-08-27
1
No Actions
Order
2026-09-03
1